Architecture manipulation

xsimd provides an high level description of the instruction sets it manipulates. The mentioned types are primarily used as template parameters for batch, and when interacting with xsimd::dispatch().

The best available architecture is available at compile time through xsimd::best_arch which also happens to be xsimd::default_arch.

group architectures

struct unavailable: #include <xsimd_arch.hpp>

Dummy architectures that only appears in a list of architecture when no other architecture has been detected.

struct generic

#include <xsimd_generic_arch.hpp>

Base class for all architectures.

Subclassed by xsimd::avx, xsimd::avx512f, xsimd::detail::rvv< Width >, xsimd::detail::sve< Width >, xsimd::neon, xsimd::sse2

Public Static Functions

static inline constexpr bool supported() noexcept: Whether this architecture is supported at compile-time.

static inline constexpr bool available() noexcept: Whether this architecture is available at run-time.

static inline constexpr std::size_t alignment() noexcept: If this architectures supports aligned memory accesses, the required alignment.

static inline constexpr bool requires_alignment() noexcept: Whether this architecture requires aligned memory access.

static inline constexpr char const *name() noexcept: Name of the architecture.

struct avx2 : public xsimd::avx 

#include <xsimd_avx2_register.hpp>

AVX2 instructions.

Subclassed by xsimd::fma3< avx2 >

struct avx512bw : public xsimd::avx512dq : #include <xsimd_avx512bw_register.hpp>

AVX512BW instructions.

struct avx512cd : public xsimd::avx512f 

#include <xsimd_avx512cd_register.hpp>

AVX512CD instructions.

Subclassed by xsimd::avx512dq

struct avx512dq : public xsimd::avx512cd 

#include <xsimd_avx512dq_register.hpp>

AVX512DQ instructions.

Subclassed by xsimd::avx512bw

struct avx512f : public xsimd::generic 

#include <xsimd_avx512f_register.hpp>

AVX512F instructions.

Subclassed by xsimd::avx512cd

struct avx : public xsimd::generic 

#include <xsimd_avx_register.hpp>

AVX instructions.

Subclassed by xsimd::avx2, xsimd::fma3< avx >

template<> struct fma3<avx> : public xsimd::avx : #include <xsimd_fma3_avx_register.hpp>

AVX + FMA instructions.

template<> struct fma3<avx2> : public xsimd::avx2 : #include <xsimd_fma3_avx2_register.hpp>

AVX2 + FMA instructions.

template<> struct fma3<sse4_2> : public xsimd::sse4_2 : #include <xsimd_fma3_sse_register.hpp>

SSE4.2 + FMA instructions.

struct fma4 : public xsimd::sse4_2 : #include <xsimd_fma4_register.hpp>

SSE4.2 + FMA4 instructions.

struct neon64 : public xsimd::neon : #include <xsimd_neon64_register.hpp>

NEON instructions for arm64.

struct neon : public xsimd::generic 

#include <xsimd_neon_register.hpp>

NEON instructions for arm32.

Subclassed by xsimd::neon64

template<size_t Width> struct rvv : public xsimd::generic : #include <xsimd_rvv_register.hpp>

RVV instructions (fixed vector size) for riscv.

struct sse2 : public xsimd::generic 

#include <xsimd_sse2_register.hpp>

SSE2 instructions.

Subclassed by xsimd::sse3

struct sse3 : public xsimd::sse2 

#include <xsimd_sse3_register.hpp>

SSE3 instructions.

Subclassed by xsimd::ssse3

struct sse4_1 : public xsimd::ssse3 

#include <xsimd_sse4_1_register.hpp>

SSE4.1 instructions.

Subclassed by xsimd::sse4_2

struct sse4_2 : public xsimd::sse4_1 

#include <xsimd_sse4_2_register.hpp>

SSE4.2 instructions.

Subclassed by xsimd::fma3< sse4_2 >, xsimd::fma4

struct ssse3 : public xsimd::sse3 

#include <xsimd_ssse3_register.hpp>

SSSE3 instructions.

Subclassed by xsimd::sse4_1

template<size_t Width> struct sve : public xsimd::generic : #include <xsimd_sve_register.hpp>

SVE instructions (fixed vector size) for arm64.

Emulated mode

When compiled with the macro XSIMD_WITH_EMULATED set to 1, xsimd also exhibits a specific architecture xsimd::emulated<N>, which consists of a vector of N bits emulated using scalar mode. It is mostly available for testing and debugging.